1. Field of the Invention
The present invention relates to a delay locked-loop circuit that keeps the synchronization between an external clock and an internal clock and a display apparatus employing the same.
2. Description of the Related Art
A clock generator applied in a clock synchronization system is an indispensable component circuit for keeping the synchronization between external data (such as an external clock) and an internal clock, as represented by a delay locked-loop circuit (which will be called “DLL” hereinafter). Even among the circuits included in the DLL, a delay control line that adjusts a phase shift is an important part for determining the maximum operating frequency or output jitter of the DLL (refer to JP-A-2005-006146 (Patent Document 1), for example).
FIG. 8 is a block diagram illustrating a DLL in the digital system as an example of the clock generator. The digital system is superior to the analog system from the viewpoint of the lower voltage operation and lower jitter and has been studied and developed actively in recent years. The DLL includes a phase comparator 1 that detects the phase difference between an external clock and an internal clock, an up/down counter (which will be called “counter” hereinafter) 2 that controls the delay time with output signals UP and DN from the phase comparator 1, a digital control delay line 3 that adjusts the delay time, and a clock driver 4.
In this embodiment, the counter has 4 bits, and 15 unit delay circuits (which will be called “Delay-Cells” hereinafter) are included in the digital control delay line. One, two, four and eight Delay-Cells connect to the LSB, 2nd bit, 3rd bit and MSB of a counter output signal, respectively.
FIG. 9 is a circuit diagram showing an example of the Delay-Cell included in the digital control delay line. The Delay-Cell includes inverters INV1, INV2 and INV3, switches SW1 and SW2 and capacitances C1 and C2.
The Delay-Cell switches the connection between the capacitances C1 and C2 and the delay line in accordance with the level of an n bit of the output signal from the counter 2 to implement the adjustment of the amount of delay.
FIG. 10 is a timing chart for a digital DLL. With reference to FIG. 10, the operational principle of the phase adjustment will be described. When an internal clock CLKINT lags behind an external clock CLKEXT (in the period 1), the signal DN has an “H” level, which is counted down by the counter 2. This separates the capacitances (C1 and C2 in FIG. 9) for delay adjustment one after another from the delay line and thus reduces the phase difference between the internal clocks CLKINT and the external clocks CLKEXT.
Conversely, when the internal clock CLKINT passes the external clock CLKEXT (in the period 2), the signal UP has an “H” level, which is counted up by the counter 2. This connects the capacitances (C1 and C2 in FIG. 9) for delay adjustment one after another to the delay line and thus reduces the phase difference between the external clock CLKEXT and the internal clock CLKINT.